“With the continuous development of Electronic systems, the demand for data transmission between chips and between boards is also increasing. The traditional single-ended parallel data transmission mode has long been unable to meet the requirements of current high-bandwidth applications. The release of new serial specifications such as USB 3.0, SATA 3.0, PCI-E 2.0, and the introduction of higher-speed serial-parallel/parallel-serial conversion unit (SERDES) chips have aroused the industry’s infinite expectations for high-speed differential serial data transmission.
“
Author: Li Linjun, Wang Yong
introduction
With the continuous development of electronic systems, the demand for data transmission between chips and between boards is also increasing. The traditional single-ended parallel data transmission mode has long been unable to meet the requirements of current high-bandwidth applications. The release of new serial specifications such as USB 3.0, SATA 3.0, PCI-E 2.0, and the introduction of higher-speed serial-parallel/parallel-serial conversion unit (SERDES) chips have aroused the industry’s infinite expectations for high-speed differential serial data transmission. In order to solve the huge data throughput requirements brought by the multi-antenna (MIMO) signal processing in the next-generation wireless communication base station, this paper presents a GTP unit based on Virtex-5 FPGA, which is implemented in an Advanced Telecom Computing Architecture (ATCA) chassis A design scheme for a single pair of differential lines for 3.125Gbps serial transmission.
Transmission system design
The structure of the transmission system is shown in Figure 1, which is mainly composed of two ATCA boards and an ATCA chassis backplane. A piece of FPGA is placed on each of the two ATCA boards as the two end points of the serial link, and two pairs of differential lines are used to connect between the two pieces of FPGA to form a two-way serial communication link of 3.125Gbps each. In order to verify the long-distance transmission capability of the system, two boards are placed in physical slot 1 and physical slot 14 of a 14-slot ATCA chassis. At this time, the total transmission distance is about 40 inches.
Figure 1 The overall structure of the high-speed serial transmission system
Since the backplane performance of the existing ATCA chassis cannot be changed, the main design of this article focuses on the design of the ATCA single board, mainly the stack design of the single board, the power supply design of the FPGA as the transmission end point, and the reference clock design for serial transmission. And the parameter adjustment of GTP transceiver unit inside FPGA.
Laminated design
The laminated design is the basis of other designs. The system mainly considers two aspects when designing the laminated structure: First, let all GTP transceiver differential lines be laid on the stripline signal layer instead of unilaterally coupled microstrip lines Signal layer. Although the stripline has a larger loss than the microstrip line, the impedance of the stripline is more controllable, and the coupling with the AC ground plane is better, which is conducive to the return of high-speed signals; the second is to reduce the power supply noise of the GTP unit. Three power planes are used to supply power to the three analog power supplies AVTT (terminated power), AVCC (internal circuit power), and AVPLL (PLL power) of the serial transceiver. The specific laminated structure is shown in Figure 2.
Figure 2 Design of laminated structure
Power design
The noise of GTP analog power supply is one of the important factors that affect GTP performance. In addition to distributing the three analog power supplies of GTP to a separate plane and coupled with a ground plane when designing the stack, a magnetic bead is connected in series for each power pin externally, and a 0.22 is connected in parallel. The μf capacitor forms an LC low-pass filter to filter the power supply. GTP’s analog power supply is supplied with a low-noise LDO power chip TPS74401, and the output voltage ripple is less than 50mV.
Clock design
The reference clock of a high-speed serial transceiver is another important factor that affects the quality of signal transmission. This system uses the clock synthesis chip LMK03001C with powerful clock clean function to generate the reference clock of the serial transceiver. The maximum root mean square jitter (RMS jitter) of the output clock is less than 550fs, the duty cycle is 50%, and the output clock level standard has two types: LVDS and LVPECL. The frequency of the output clock can be flexibly programmed to meet the requirements of different transmission rates, so that the system can adapt to the realization of multiple serial transmission protocols.
Pre/de-emphasis and equalization parameter design
In order to counter the excessive attenuation of high-frequency components by the transmission path, it is necessary to perform pre-emphasis at the transmitting end or add equalization at the receiving end or use both methods at the same time. Pre/de-emphasis and linear equalization both improve the quality of the received signal by distorting the signal. Only a suitable ratio of pre/de-emphasis and linear equalization and the combination between the two can achieve the purpose of improving the quality of the received signal. Otherwise, On the contrary, it will deteriorate the quality of the received signal. This article uses the SPICE model of GTP and the S-parameter model of the serial transmission channel to simulate the transmission quality of the serial link under different pre/de-emphasis and equalization parameter settings to find out the appropriate parameter settings.
Figure 3 Transmit signals under different pre/de-emphasis ratios
Figure 3 shows the simulation results under different pre/de-emphasis settings. The middle part shows the transmission waveform of three consecutive high-level bits. Obviously, the amplitude of the latter two high-level bits decreases correspondingly with the ratio of pre/de-emphasis. In addition, the signal level in the same logic bit in the figure is not flat. This phenomenon is mainly caused by the transmission caused by the impedance mismatch on the signal transmission link, such as the connector of the ATCA single board and the ATCA backplane. Junction.
Figure 4 The influence of pre/de-emphasis and equalization on the received signal
Figure 4 shows the eye diagrams of GTP received signals under different parameter settings. The first sub-picture is the signal eye diagram on the FPGA pin at the receiving end without pre-/de-emphasis applied at the transmitting end. It can be seen that long-distance transmission seriously deteriorates the quality of the signal, and the signal eye diagram tends to close. The second sub-picture is the signal eye diagram on the FPGA pin at the receiving end when 23% pre/de-emphasis is applied at the transmitting end. Pre/de-emphasis compensates for the low-pass characteristics of the transmission channel to a certain extent, reduces the jitter of the signal, and improves the quality of the signal. The third sub-picture shows that the transmitting end does not apply pre/de-emphasis and 25% equalization is applied to the receiving end, that is, 75% of the original signal plus 25% of the high-pass filter output is used as the total received signal. Like pre/de-emphasis, through equalization, high-frequency components are relatively enhanced, and low-frequency components are relatively suppressed, which effectively compensates for channel imperfections. The fourth sub-picture is the received signal obtained when 4.5% pre/de-emphasis and 25% equalization work simultaneously. It can be seen that the effective combination of pre/de-emphasis and equalization can well improve the originally severely degraded transmission signal.
Figure 5 Measured serial signal eye diagram
Validation and discussion of results
The performance test of this system is mainly carried out in two ways: one is to collect the signal eye diagram of the transceiver and compare it with the receiver’s mask (EYE_MASK); the other is to test the bit error rate of serial transmission (BERT: bit error). ratio test).
The EYE_MASK of the receiver vividly reflects the sensitivity and dynamic range of the receiver, and only the signal in the receiving area can be correctly identified by the receiver, otherwise the error code will be obtained after sampling and judgment. The minimum EYE_MASK of the GTP unit in Virtex-5 is (112ps, 150mV), where 112ps represents the minimum eye width (EYE_WIDTH), and 150mV gives the minimum eye height (EYE_HEIGHT). Figure 5 shows the signals at both ends of the serial transmission that are measured near the FPGA transmit and receive pins. In this test channel environment, the normal transmission signal has been greatly attenuated and distorted when it reaches the receiving end. The eye width is only 96ps and the eye height is only 70.5mV, which does not meet the requirements of GTP (112ps, 150mV). If the equalizer inside the chip is not considered, the received signal will not be correctly identified. On the contrary, if pre-/de-emphasis is added at the transmitting end, it can effectively combat the undesirability of the channel, reduce the jitter of the receiving signal to a certain extent, and open the eye pattern to (211ps, 191mV). This measured result is consistent with the previous simulation and theoretical analysis.
Xilinx provides a tool for bit error rate testing, IBERT, as shown in Figure 6. The basic principle is to send a pseudo-random sequence (such as PRBS7) at the transmitting end, and then connect it with the same pseudo-random sequence at the receiving end. Proofread the random sequence and record the results of the proofreading. Use this tool to dynamically adjust the GTP parameter settings and measure the corresponding transmission error rate.
Figure 6 Bit error rate test
Through the IBERT tool, the error-free (BER<1e-12) sampling interval of this system under different pre/de-emphasis and equalization parameter settings can be obtained, as shown in Table 1.
Table 1 Error-free sampling interval (unit: 1/128 UI)
The Links: LM1180TGR QM100DY-2H GET PARTS
